My name is Anton. I am 26 years old. I work Design Verification Engineer in the field of ASIC and FPGA. I always like to expand new boundaries of knowledge for myself and explore new technologies
Overview
6
6
years of professional experience
Work History
Software Validation Engineer
Artec 3D
Luxembourg
09.2024 - Current
Linux Kernel Customisation and configuration (ARM platform)
Experience working with Linux systems (file systems, network, device drivers, device tree)
UEFI configuration and compilation
Bringing up firmware for prototyping board FPGA + GPU(NVidia Jetson Nano)
ASIC/FPGA/SoC Design Verification Engineer
Artec 3D
Luxembourg
07.2022 - Current
Verify Image Signal Processing pipeline of 3D scanner using Python + OpenCV and C++ golden models
Test bench and infrastructure development using SystemVerilog/UVM/CocoTB
IP level test development using SystemVerilog/UVM/CocoTB (for blocks like DMA, JPEG-LS, detectors, decoders, bayer process, etc.)
Industry standard protocols, such as AMBA (AHB/APB/AXI4), I2C, SPI
Created verification environment
Work with RDL (Register Description Language)
Top level SoC simulation with MicroBlaze
Using Xcelium and vManager
Created CI/CD regression system for full Computer Vision pipeline for 3D scanner on Jenkins
Synopsis PCIe IP cores generation (coreConsultant)
PCIe verification (environment with root complex and end point devices)
VIPs from vendors(VIPCAT Cadence)
Senior Design Verification Engineer - Consultant
MaltSystem
02.2024 - 02.2025
Set up verification flow
Set up UVM verification structure and enviroment
Block level verification and top level verification(SoC)
ASIC Design Verification Engineer
ON Semiconductor
Saint Petersburg
11.2021 - 07.2022
Quantenna Communications division
Verifiction and automation of the hardware for wi-fi chip
Creating a UVC's
Creating VIP's
Designing test plan for verification
Coding test scenarios, assertion and debugging for Digital Design
Creating check points for C 'golden' model
Constraint-based random verification
Creating unit UVM testbenches
Development of Python scripts to automate the development process (subprocess, logging, pathlib, etc.)
Code coverage and function coverage analysis
Writing C++ wrappers for C models
Description of C++ wrappers for the DPI interface
Using VRM for regression test's
GLS, UPF
Using QUEMU to test software on an ARM core
Worked with 802.11ax and 802.11be (Wi-Fi 6 and Wi-Fi 7) standart for verify baseband part of WiFi chip
Working with version control system (SOS, Git)
Strong knowledge of Linux at the developer level
Work in project management system Jira, Confluence
ASIC Design Verification Engineer
MaltSystem
Moscow
11.2020 - 11.2021
Development of peripheral blocks on VHDL/Verilog/ Verification and Design NPU chip
SDF verification(posttopological)
Cocotb(Python verification)
C++ and Python 'golden' models
Testing blocks with AXI interfaces(AXILite, AXIStream, AXI4)
Blocks with interfaces RGMII, MII, GMII, UART, SPI, I2C, etc
Python flow development
Code coverage and Functional coverage
Working with version control systems (Mercurial, Git)
Working with the Jenkins
Confident knowledge of Linux at the user level
Design And Development Engineer
All -Russian Scientific Research Institute of Radio Engineering (VNIIRT)
Moscow
08.2019 - 10.2020
Work in projects containing microcontrollers, FPGAs and external interfaces
Development of electronics with the content of high-speed interfaces (USB, SATA)
Development of a library of graphical symbols and a library of seats for ERI in Altium Designer
Development of the PC topology
Conducting output testing of RTL descriptions in ModelSim
Development of TCL scripts
Checking the integrity of signals in the HyperLynx program
Modeling the operation of REA modules
Ability to work with modern measuring devices (Agilent, Tektronix)
Education
Master of Science - Radio Electronic Systems and Complexes
Moscow Aviation Institute (National Research University)
Moscow
01.2022
Skills
Linux
Jira
Git
Bash
SystemVerilog
Python
DevOps
Jenkins
C
Languages
Russian, Native speaker
English, Highly proficient
Personal Information
Age: 26
Title: ASIC Design Verification Engineer
Timeline
Software Validation Engineer
Artec 3D
09.2024 - Current
Senior Design Verification Engineer - Consultant
MaltSystem
02.2024 - 02.2025
ASIC/FPGA/SoC Design Verification Engineer
Artec 3D
07.2022 - Current
ASIC Design Verification Engineer
ON Semiconductor
11.2021 - 07.2022
ASIC Design Verification Engineer
MaltSystem
11.2020 - 11.2021
Design And Development Engineer
All -Russian Scientific Research Institute of Radio Engineering (VNIIRT)
08.2019 - 10.2020
Master of Science - Radio Electronic Systems and Complexes
Moscow Aviation Institute (National Research University)